SCLK – Main clock synchronizing SPI on both devices. Generated by the Master to all the slaves
MOSI – Master Output and Slave Input in which data is sent from the master to the slave on each clock edge
MISO – Master Input and Slave Output in which data is sent from the slave to the master on each clock edge
SS – Slave select, often called CS (Chip Select) or CSn. This line selects the current active slave. It could be Active Low or Active high (refer to the slave datasheet)
SPI Modes- Phase (PH) and Polarity (POL) bits
CPHA/CKPH = 0, Read on the leading edge of each clock pulse. Written on the trailing edge of each clock pulse.
CPHA/ CKPH = 1 , Written on the leading edge of each clock pulse. Read on the trailing edge of each clock pulse.