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====== MSP430: Clock Systems and Timers ======

{{ :microcontrollers:clock1.png?direct&600 |}}

**Benefits:**

  * Low clk freq. for energy conservation and time keeping
  * High clk freq. for fast burst processing capabilities/response time
  * Low-cost applications with less-constrained clk accuracy requirement
  * Allows user to select best balance of performance and power consumption.

Clock module can operate with or without external components like crystals and resonators.

===== Clock Sources =====

==== External ====

**LFXTCLK** 
  * Low-frequency oscillator.
  * Powered by a 32768 Hz crystal, resonators or external clock sources (<= 50KHz) in bypass mode.
**HFXTCLK** 
  * High-frequency oscillator.
  * Used with crystals or resonators in the 4-MHz to 24-MHz range, and can be driven with an external square wave signal.

==== Internal ====

**VLOCLK** 
  * Internal very-low-power low-frequency oscillator.
  * 10 KHz typical frequency.
  * Low-cost clk source for applications without high timing accuracy req.
**DCOCLK** 
  * Internal digitally controlled oscillator.
  * With selectable frequencies: 1 - 24 MHz
**MODCLK** 
  * Internal low-power module oscillator.
  * 5 KHz typical frequency. It gives LFMODCLK when divided by 128

===== Clock Signals =====

**Master Clock (MCLK) ** 
  * Software selectable as LFXTCLK, VLOCLK, MODCLK,  DCOCLK or HFXTCLK.
  * Can be divided by 1,2,4,8,16 or 32.
  * Used by the CPU and the system.
**Subsystem Master Clock (SMCLK) ** 
  * Software selectable as LFXTCLK, VLOCLK, MODCLK,  DCOCLK or HFXTCLK.
  * Used by peripheral modules.
**Auxiliary Clock (ACLK) ** 
  * Software selectable as LFXTCLK, VLOCLK or LFMODCLK.
  * Can be divided by 1,2,4,8,16 or 32.
  * Used by peripheral modules.
**Module Clock (MODCLK) ** 
  * Sourced by MODOSC.
  * Used by various peripheral modules.
**VLO Clock (VLOCLK)**  
  * Sourced by VLO.
  * Used directly by various peripheral modules.

Clock source for each clock signal is selected using the SEL register. 
ACLK, MCLK and SMCLK use SELAx, SELMx, and SELSx respectively to select clock source.

===== Clock Configuration =====

There are 7 Clk system control registers: 
  * CSCTL0: Enables access control to other registers when correct password key is set. e.g.  CSCTL0 = CSKEY 
  * CSCTL1: Enables DCO range and frequency selection (DCORSEL & DCOFSEL)
  * CSCTL2: Used for setting clock source for ACLK, MCLK and SMCLK.
  * CSCTL3: Used setting frequency divider for those clock sources. It could be 1,2,4,8,16 or 32.
  * CSCTL4: Sets the HFXT and LFXT oscillator ON or OFF.